As the speed of silicon circuits continues to increase, bus timings are becoming a limiting factor in system performance. Frequently, semiconductor chips could operate at internal frequencies that are multiples of the external system clock frequency rate. This is especially true for microprocessors that contain on-board instruction and data cache since such processors can carry out multiple machine cycles without need to reference information via an external bus.
Existing approaches to accomplishing clock signal frequency multiplication typically employ an analog phase locked loop or a digital phase locked loop. Unfortunately, such circuits can be difficult to design and implement. (For example, analog phase locked loops often require components external to the semiconductor chip.) Thus, there is a genuine need in the art for a more practical approach to on-chip clock signal frequency multiplication for enhancing chip processing performance.